1. Field of the Invention
The present invention relates to a digital camera, and more particularly, to an improved analog signal processing apparatus for a digital camera which is capable of carrying out a black level clamping with regard to a digital-converted image signal.
2. Description of the Background Art
In general, in a digital camera, the light from a lens is converted into an electrical signal via a charge coupled device (CCD). The converted electrical signal is sampled using a black level as a reference to generate a typical video signal which is then converted to a digital image signal via respective signal processing steps. Eventually, the converted digital image signal is outputted via a digital signal processor (DSP).
The digital signal converting process of carrying out the respective signal processing steps with regard to the analog signal will now be described with reference to the accompanying drawings.
As shown in FIG. 1, a conventional analog signal processing apparatus for a digital camera includes a correlated double sampling (CDS) circuit 10 adjusting a direct current (DC) level of an electrical signal from a CCD (not shown) by using a black level as a reference and converting the DC level electrical signal into a typical video signal, an automatic gain control (AGC) circuit 20 adjusting the gain of the output signal of the CDS circuit 10 and outputting a signal amplified by as much as a predetermined gain, an analog-to-digital (A/D) converter 30 converting the analog signal from the AGC circuit 20 into a digital signal and outputting the converted signal to a DSP (not shown), and a black level clamp circuit 40 comparing a black level signal from the AGC circuit 20 and a preset black level reference value VREF and carrying out a black level clamping.
The black level clamp circuit 40 includes a switch 41 connected to an output of the AGC circuit 20 and turned on/off under the control of a black level clamping signal BLKCLP outputted at time intervals from a clock generator (not shown), an analog comparator 42 comparing a signal corresponding to the black level from the AGC circuit 20 and the preset black level reference value VREF in accordance with the turning on of the switch 41, and an integrator 43 determining an accurate black level required to the CDS circuit 10 in accordance with the compared result and applying the same to the CDS circuit 10.
The analog signal processing steps for the conventional digital camera will now be explained.
The signal from the CCD is converted into a typical video signal via the CDS circuit 10. At this time, the DC voltage of the video signal is adjusted with reference to a black level.
Here, the black level is adjusted at predetermined time intervals in accordance with the output of the black level clamp circuit 40.
The video signal formed by the CDS circuit 10 is applied to the AGC circuit 20 and amplified therein depending upon a gain value, and then converted into a digital video signal in the A/D converter 30.
Meanwhile, the switch 41 provided at the output terminal of the AGC circuit 20 is turned on/off in accordance with the black level clamping signal BLKCLP received at predetermined time intervals from the clock generator (not shown), and it transmits the output signal of the AGC circuit 20 to the analog comparator 42.
As shown in FIG. 2, the black level clamping signal BLKCLP becomes active during non-image intervals B which occur between respective lines of a camera scan.
In the intervals B where the black level clamping signal BLKCLP becomes active, the switch 41 is turned on and accordingly a signal outputted from the AGC circuit 20 and corresponding to a black level is applied to the analog comparator 42.
Then, the analog comparator 42 compares the present black level signal from the AGC circuit 20 and the preset black level reference value VREF. The integrator 43 levels up or down the black level value according to the compared result and feeds back the same to the CDS circuit 10.
As a result, when the CDS circuit 10 converts the electrical signal which is received from the CCD into a video signal in accordance with the output signal of the integrator 43 to a video signal, the black level as its reference is accurately corrected and the DC voltage level of the video signal is adjusted, accordingly.
As described above, in the conventional digital camera, it is difficult to maintain the preset black level due to error factors such as a process error and an offset which occur in respective blocks inside the system, so that the black level clamping circuit 40 is provided which clamps the black level at predetermined time intervals for its solution.
However, the conventional black level clamp circuit 40 has difficulty in solving the offset voltage generated from the analog comparator 42 or the integrator 43 in the black level clamp circuit 40, or the A/D converter 30 operating after the clamping performance. In order to solve the above drawbacks, an additional compensation block should be disadvantageously included in an initial circuit design.
The present invention is directed to overcoming the conventional disadvantages.
Therefore, it is an object of the present invention to provide an analog signal processing apparatus for a digital camera, capable of carrying out a black level clamping with regard to a digital-converted image signal.
To achieve the above-described object, there is provided an analog signal processing apparatus for a digital camera according to the present invention which includes a correlated double sampling (CDS) circuit adjusting a direct current (DC) level signal from a charge coupled device (CCD) by using a black level as a reference and converting the DC level signal to a typical video signal, an automatic gain control (AGC) circuit automatically adjusting the gain of an output signal of the CDS circuit, an analog-to-digital (A/D) converter converting the analog signal from the AGC circuit into a digital signal, a black level clamp circuit clamping the black level of a digital image signal from the A/D converter for a predetermined time interval and feeding back the same to the CDS circuit, and a clock generator generating first and second clock signals and a black level clamping signal so as to control the timing of the black level clamp circuit.
The features and advantages of the present invention will become more readily apparent from the detailed description given hereinafter. However, it should be understood that the detailed description and specific example, while indicating preferred embodiments of the invention, are given by way of illustration only, since various changes and modifications within the spirit and scope of the invention will become apparent to those skilled in the art from this detailed description.